From ad691931c6e000d74f57780305295653385c0da4 Mon Sep 17 00:00:00 2001
From: deltanedas <39013340+deltanedas@users.noreply.github.com>
Date: Sun, 18 Aug 2024 22:34:43 +0000
Subject: [PATCH] add memory cell and rework logic construction (#24983)

* rework construction to be deconstructable, add memory cell

* update textures

* add code

* add memory cell and ports, empty circuit

* d

---------

Co-authored-by: deltanedas <@deltanedas:kde.org>
---
 .../Components/MemoryCellComponent.cs         |  40 +++++++++
 .../DeviceLinking/Systems/MemoryCellSystem.cs |  74 +++++++++++++++
 .../en-US/machine-linking/receiver_ports.ftl  |   5 ++
 .../Prototypes/DeviceLinking/sink_ports.yml   |  10 +++
 .../Prototypes/Entities/Structures/gates.yml  |  49 ++++++++--
 .../Construction/Graphs/tools/logic_gate.yml  |  84 ++++++++++++++++--
 .../Prototypes/Recipes/Construction/tools.yml |  11 +++
 .../Objects/Devices/gates.rsi/base.png        | Bin 7579 -> 7307 bytes
 .../Devices/gates.rsi/edge_detector.png       | Bin 7375 -> 7036 bytes
 .../Objects/Devices/gates.rsi/logic.png       | Bin 0 -> 7196 bytes
 .../Objects/Devices/gates.rsi/memory_cell.png | Bin 0 -> 228 bytes
 .../Objects/Devices/gates.rsi/meta.json       |   8 +-
 .../Devices/gates.rsi/power_sensor.png        | Bin 7376 -> 7090 bytes
 13 files changed, 264 insertions(+), 17 deletions(-)
 create mode 100644 Content.Server/DeviceLinking/Components/MemoryCellComponent.cs
 create mode 100644 Content.Server/DeviceLinking/Systems/MemoryCellSystem.cs
 create mode 100644 Resources/Textures/Objects/Devices/gates.rsi/logic.png
 create mode 100644 Resources/Textures/Objects/Devices/gates.rsi/memory_cell.png

diff --git a/Content.Server/DeviceLinking/Components/MemoryCellComponent.cs b/Content.Server/DeviceLinking/Components/MemoryCellComponent.cs
new file mode 100644
index 0000000000..d55042978a
--- /dev/null
+++ b/Content.Server/DeviceLinking/Components/MemoryCellComponent.cs
@@ -0,0 +1,40 @@
+using Content.Server.DeviceLinking.Systems;
+using Content.Shared.DeviceLinking;
+using Robust.Shared.Prototypes;
+
+namespace Content.Server.DeviceLinking.Components;
+
+/// <summary>
+/// Memory cell that sets the output to the input when enabled.
+/// </summary>
+[RegisterComponent, Access(typeof(MemoryCellSystem))]
+public sealed partial class MemoryCellComponent : Component
+{
+    /// <summary>
+    /// Name of the input port.
+    /// </summary>
+    [DataField]
+    public ProtoId<SinkPortPrototype> InputPort = "MemoryInput";
+
+    /// <summary>
+    /// Name of the enable port.
+    /// </summary>
+    [DataField]
+    public ProtoId<SinkPortPrototype> EnablePort = "MemoryEnable";
+
+    /// <summary>
+    /// Name of the output port.
+    /// </summary>
+    [DataField]
+    public ProtoId<SourcePortPrototype> OutputPort = "Output";
+
+    // State
+    [DataField]
+    public SignalState InputState = SignalState.Low;
+
+    [DataField]
+    public SignalState EnableState = SignalState.Low;
+
+    [DataField]
+    public bool LastOutput;
+}
diff --git a/Content.Server/DeviceLinking/Systems/MemoryCellSystem.cs b/Content.Server/DeviceLinking/Systems/MemoryCellSystem.cs
new file mode 100644
index 0000000000..56a6f45c3b
--- /dev/null
+++ b/Content.Server/DeviceLinking/Systems/MemoryCellSystem.cs
@@ -0,0 +1,74 @@
+using Content.Server.DeviceLinking.Components;
+using Content.Server.DeviceLinking.Events;
+using Content.Server.DeviceNetwork;
+using Content.Shared.DeviceLinking;
+
+namespace Content.Server.DeviceLinking.Systems;
+
+/// <summary>
+/// Handles the control of output based on the input and enable ports.
+/// </summary>
+public sealed class MemoryCellSystem : EntitySystem
+{
+    [Dependency] private readonly DeviceLinkSystem _deviceLink = default!;
+
+    public override void Initialize()
+    {
+        base.Initialize();
+
+        SubscribeLocalEvent<MemoryCellComponent, ComponentInit>(OnInit);
+        SubscribeLocalEvent<MemoryCellComponent, SignalReceivedEvent>(OnSignalReceived);
+    }
+
+    public override void Update(float deltaTime)
+    {
+        base.Update(deltaTime);
+
+        var query = EntityQueryEnumerator<MemoryCellComponent, DeviceLinkSourceComponent>();
+        while (query.MoveNext(out var uid, out var comp, out var source))
+        {
+            if (comp.InputState == SignalState.Momentary)
+                comp.InputState = SignalState.Low;
+            if (comp.EnableState == SignalState.Momentary)
+                comp.EnableState = SignalState.Low;
+
+            UpdateOutput((uid, comp, source));
+        }
+    }
+
+    private void OnInit(Entity<MemoryCellComponent> ent, ref ComponentInit args)
+    {
+        var (uid, comp) = ent;
+        _deviceLink.EnsureSinkPorts(uid, comp.InputPort, comp.EnablePort);
+        _deviceLink.EnsureSourcePorts(uid, comp.OutputPort);
+    }
+
+    private void OnSignalReceived(Entity<MemoryCellComponent> ent, ref SignalReceivedEvent args)
+    {
+        var state = SignalState.Momentary;
+        args.Data?.TryGetValue(DeviceNetworkConstants.LogicState, out state);
+
+        if (args.Port == ent.Comp.InputPort)
+            ent.Comp.InputState = state;
+        else if (args.Port == ent.Comp.EnablePort)
+            ent.Comp.EnableState = state;
+
+        UpdateOutput(ent);
+    }
+
+    private void UpdateOutput(Entity<MemoryCellComponent, DeviceLinkSourceComponent?> ent)
+    {
+        if (!Resolve(ent, ref ent.Comp2))
+            return;
+
+        if (ent.Comp1.EnableState == SignalState.Low)
+            return;
+
+        var value = ent.Comp1.InputState != SignalState.Low;
+        if (value == ent.Comp1.LastOutput)
+            return;
+
+        ent.Comp1.LastOutput = value;
+        _deviceLink.SendSignal(ent, ent.Comp1.OutputPort, value, ent.Comp2);
+    }
+}
diff --git a/Resources/Locale/en-US/machine-linking/receiver_ports.ftl b/Resources/Locale/en-US/machine-linking/receiver_ports.ftl
index dc45677c8d..a0d2fd3ec4 100644
--- a/Resources/Locale/en-US/machine-linking/receiver_ports.ftl
+++ b/Resources/Locale/en-US/machine-linking/receiver_ports.ftl
@@ -81,3 +81,8 @@ signal-port-description-logic-input-b = Second input of a logic gate.
 
 signal-port-name-logic-input = Input
 signal-port-description-logic-input = Input to the edge detector, cannot be a pulse signal.
+
+signal-port-description-logic-memory-input = Signal to load into the memory cell, when enabled.
+
+signal-port-name-logic-enable = Enable
+signal-port-description-logic-enable = Only loads the input signal into the memory cell when HIGH.
diff --git a/Resources/Prototypes/DeviceLinking/sink_ports.yml b/Resources/Prototypes/DeviceLinking/sink_ports.yml
index 56b10ec4fc..339b814175 100644
--- a/Resources/Prototypes/DeviceLinking/sink_ports.yml
+++ b/Resources/Prototypes/DeviceLinking/sink_ports.yml
@@ -93,6 +93,16 @@
   name: signal-port-name-logic-input
   description: signal-port-description-logic-input
 
+- type: sinkPort
+  id: MemoryInput
+  name: signal-port-name-logic-input
+  description: signal-port-description-logic-memory-input
+
+- type: sinkPort
+  id: MemoryEnable
+  name: signal-port-name-logic-enable
+  description: signal-port-description-logic-enable
+
 - type: sinkPort
   id: SetParticleDelta
   name: signal-port-name-set-particle-delta
diff --git a/Resources/Prototypes/Entities/Structures/gates.yml b/Resources/Prototypes/Entities/Structures/gates.yml
index 6b02840ba0..8e60962321 100644
--- a/Resources/Prototypes/Entities/Structures/gates.yml
+++ b/Resources/Prototypes/Entities/Structures/gates.yml
@@ -1,12 +1,24 @@
 - type: entity
-  abstract: true
   parent: BaseItem
-  id: BaseLogicItem
+  id: LogicEmptyCircuit
+  name: empty circuit
+  description: Something seems to be missing.
   components:
   - type: Sprite
     sprite: Objects/Devices/gates.rsi
+    layers:
+    - state: base
   - type: Anchorable
   - type: Rotatable
+  - type: Construction
+    graph: LogicGate
+    node: empty
+
+- type: entity
+  abstract: true
+  parent: LogicEmptyCircuit
+  id: BaseLogicItem
+  components:
   - type: DeviceNetwork
     deviceNetId: Wireless
     receiveFrequencyId: BasicDevice
@@ -23,6 +35,7 @@
   - type: Sprite
     layers:
     - state: base
+    - state: logic
     - state: or
       map: [ "enum.LogicGateLayers.Gate" ]
   - type: LogicGate
@@ -38,7 +51,6 @@
     lastSignals:
       Output: false
   - type: Construction
-    graph: LogicGate
     node: logic_gate
   - type: Appearance
   - type: GenericVisualizer
@@ -124,7 +136,9 @@
   description: Splits rising and falling edges into unique pulses and detects how edgy you are.
   components:
   - type: Sprite
-    state: edge_detector
+    layers:
+    - state: base
+    - state: edge_detector
   - type: EdgeDetector
   - type: DeviceLinkSink
     ports:
@@ -137,7 +151,6 @@
       OutputHigh: false
       OutputLow: false
   - type: Construction
-    graph: LogicGate
     node: edge_detector
 
 - type: entity
@@ -147,7 +160,9 @@
   description: Generates signals in response to powernet changes. Can be cycled between cable voltages.
   components:
   - type: Sprite
-    state: power_sensor
+    layers:
+    - state: base
+    - state: power_sensor
   - type: PowerSensor
   - type: PowerSwitchable
     examineText: power-sensor-voltage-examine
@@ -183,5 +198,25 @@
       PowerCharging: false
       PowerDischarging: false
   - type: Construction
-    graph: LogicGate
     node: power_sensor
+
+- type: entity
+  parent: BaseLogicItem
+  id: MemoryCell
+  name: memory cell
+  description: A D-Latch circuit that stores a signal which can be changed depending on input and enable ports.
+  components:
+  - type: Sprite
+    layers:
+    - state: base
+    - state: memory_cell
+  - type: MemoryCell
+  - type: DeviceLinkSink
+    ports:
+    - MemoryInput
+    - MemoryEnable
+  - type: DeviceLinkSource
+    ports:
+    - Output
+  - type: Construction
+    node: memory_cell
diff --git a/Resources/Prototypes/Recipes/Construction/Graphs/tools/logic_gate.yml b/Resources/Prototypes/Recipes/Construction/Graphs/tools/logic_gate.yml
index d366a2ea59..37c85e07a3 100644
--- a/Resources/Prototypes/Recipes/Construction/Graphs/tools/logic_gate.yml
+++ b/Resources/Prototypes/Recipes/Construction/Graphs/tools/logic_gate.yml
@@ -4,38 +4,104 @@
   graph:
   - node: start
     edges:
-    - to: logic_gate
+    - to: empty
       steps:
       - material: Steel
         amount: 3
         doAfter: 1
+  - node: empty
+    entity: LogicEmptyCircuit
+    edges:
+    - to: start
+      steps:
+      - tool: Screwing
+        doAfter: 2
+      completed:
+      - !type:SpawnPrototype
+        prototype: SheetSteel1
+        amount: 3
+      - !type:DeleteEntity {}
+    - to: logic_gate
+      steps:
       - material: Cable
         amount: 2
         doAfter: 1
     - to: edge_detector
       steps:
-      - material: Steel
-        amount: 3
+      - material: Glass
+        amount: 2
         doAfter: 1
       - material: Cable
         amount: 2
         doAfter: 1
     - to: power_sensor
       steps:
-      - material: Steel
-        amount: 3
-        doAfter: 1
-      - material: Cable
-        amount: 2
-        doAfter: 1
       - tag: Multitool
         icon:
           sprite: Objects/Tools/multitool.rsi
           state: icon
         name: a multitool
+      - material: Cable
+        amount: 2
+        doAfter: 1
+    - to: memory_cell
+      steps:
+      - tag: CapacitorStockPart
+        icon:
+          sprite: Objects/Misc/stock_parts.rsi
+          state: capacitor
+        name: a capacitor
+      - material: Cable
+        amount: 2
+        doAfter: 1
   - node: logic_gate
     entity: LogicGateOr
+    edges:
+    - to: empty
+      steps:
+      - tool: Prying
+        doAfter: 2
+      completed:
+      - !type:SpawnPrototype
+        prototype: CableApcStack1
+        amount: 2
   - node: edge_detector
     entity: EdgeDetector
+    edges:
+    - to: empty
+      steps:
+      - tool: Prying
+        doAfter: 2
+      completed:
+      - !type:SpawnPrototype
+        prototype: SheetGlass1
+        amount: 2
+      - !type:SpawnPrototype
+        prototype: CableApcStack1
+        amount: 2
   - node: power_sensor
     entity: PowerSensor
+    edges:
+    - to: empty
+      steps:
+      - tool: Prying
+        doAfter: 2
+      completed:
+      - !type:SpawnPrototype
+        prototype: Multitool
+      - !type:SpawnPrototype
+        prototype: CableApcStack1
+        amount: 2
+  - node: memory_cell
+    entity: MemoryCell
+    edges:
+    - to: empty
+      steps:
+      - tool: Prying
+        doAfter: 2
+      completed:
+      - !type:SpawnPrototype
+        prototype: CapacitorStockPart
+      - !type:SpawnPrototype
+        prototype: CableApcStack1
+        amount: 2
diff --git a/Resources/Prototypes/Recipes/Construction/tools.yml b/Resources/Prototypes/Recipes/Construction/tools.yml
index a6d9e33f4c..bb89c5f244 100644
--- a/Resources/Prototypes/Recipes/Construction/tools.yml
+++ b/Resources/Prototypes/Recipes/Construction/tools.yml
@@ -41,3 +41,14 @@
   description: A power network checking device for signals.
   icon: { sprite: Objects/Devices/gates.rsi, state: power_sensor }
   objectType: Item
+
+- type: construction
+  name: memory cell
+  id: MemoryCell
+  graph: LogicGate
+  startNode: start
+  targetNode: memory_cell
+  category: construction-category-tools
+  description: A memory cell for signals.
+  icon: { sprite: Objects/Devices/gates.rsi, state: memory_cell }
+  objectType: Item
diff --git a/Resources/Textures/Objects/Devices/gates.rsi/base.png b/Resources/Textures/Objects/Devices/gates.rsi/base.png
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diff --git a/Resources/Textures/Objects/Devices/gates.rsi/memory_cell.png b/Resources/Textures/Objects/Devices/gates.rsi/memory_cell.png
new file mode 100644
index 0000000000000000000000000000000000000000..bcb0d509b96affd4bf078ac7d4fa3c54ae94b59d
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diff --git a/Resources/Textures/Objects/Devices/gates.rsi/meta.json b/Resources/Textures/Objects/Devices/gates.rsi/meta.json
index 9d10f53279..761bdab87a 100644
--- a/Resources/Textures/Objects/Devices/gates.rsi/meta.json
+++ b/Resources/Textures/Objects/Devices/gates.rsi/meta.json
@@ -1,7 +1,7 @@
 {
   "version": 1,
   "license": "CC-BY-SA-3.0",
-  "copyright": "or.png originally created by Kevin Zheng, 2022. All are modified by deltanedas (github) for SS14, 2023.",
+  "copyright": "or.png originally created by Kevin Zheng, 2022. All are modified by deltanedas (github) for SS14, 2024.",
   "size": {
     "x": 32,
     "y": 32
@@ -10,6 +10,9 @@
     {
       "name": "base"
     },
+    {
+      "name": "logic"
+    },
     {
       "name": "or"
     },
@@ -36,6 +39,9 @@
     },
     {
       "name": "power_sensor"
+    },
+    {
+      "name": "memory_cell"
     }
   ]
 }
diff --git a/Resources/Textures/Objects/Devices/gates.rsi/power_sensor.png b/Resources/Textures/Objects/Devices/gates.rsi/power_sensor.png
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-- 
2.51.2